276 Programmable Logic Controllers: Hardware and Programming
Allen-Bradley SLC 500 series programmable logic controllers
have four logic gate instructions: NOT, AND, OR, and XOR. In this
chapter, you will learn how to use these four instructions to perform
the operations of logic gates for the sixteen-bit data bit files in a PLC
system.
There are two groups of internal bit data files in the SLC 500 PLC
system. These data bit files are B3 and B10. Each data bit file contains
256 words. This means that Allen-Bradley SLC 500 series PLCs have
B3:0 through B3:255 and B10:0 through B10:255 internal 16-bit words.
Therefore, SLC 500 series programmable logic controllers have 512
internal 16-bit words for a total of 512 × 16 = 8,192 bits. Each internal
bit can be used to control one internal coil. The contacts associated
with these internal coils are used to turn on or turn off output devices.
Notice that data bit files are referred to by B3 or B10 labels. However,
each bit in the data bit file is labeled independently (e.g., B3/1, B3/2,
B10/1, and B10/2). It should also be noted that one can reference each
bit as B3/17 or B3:1/1. B3/17 means that you want to use the 17th bit in
file B3 which is the same as bit one in word B3:1 (i.e., B3:1/1).
In this chapter, you will also learn how to use the bit shift instruc-
tions of a PLC device to rotate bits through an internal bit data file.
Allen-Bradley SLC 500 series PLCs have two bit shift instructions.
These bit shift instructions are bit shift left (BSL) and bit shift right
(BSR). In this chapter, you will learn how to use these instructions in
ladder logic diagrams.
13.2 Logic Gate Instructions
Allen-Bradley SLC 500 series PLCs have four logic gate instruc-
tions: NOT, AND, OR, and XOR. Figure 13-1 displays the logic gate
instructions. The instructions carry out the operation for sixteen-bit
internal bit data file words.
As discussed in Chapter 7, the NOT, or invert, instruction converts
a logic high (1) to a logic low (0) and vice versa. The AND instruction
generates a logic low (0) whenever one of the corresponding bits is 0.
The OR instruction generates a logic high (1) whenever at least one of
the corresponding bits is 1. The XOR instruction generates a logic high
(1) whenever the two corresponding bits in the word do not match.
Figure 13-2 displays the 16-bit words in bit data file B3 used for the
logic instructions displayed in Figure 13-1. Input words and the result
of the logic instructions’ operations are displayed in Figure 13-2. For
example, the result of logical AND for data words B3:2 and B3:3 are in
the data word B3:4.
The NAND, NOR, and XNOR logic instructions are built by
inverting the AND, OR, and XOR instructions respectively. Exam-
ine Figures 13-3, 13-4, and 13-5. These figures display how to cre-
ate NAND, NOR, and XNOR logic instructions respectively. After