Chapter 13 PLC Logic and Bit Shift Instructions 281
Control register (R6):
Holds status flag bits.
Reset (RES)
instruction:
An instruction used with
bit shift instructions to
reset to the original bit.
In the bit shift left instruction, a control register must be used to
hold the status flag bits. PLCs use the status flag bits in control regis-
ters to monitor and control the shift instruction. Registers in data file
control register (R6) are used as control registers. These control reg-
isters are R6:0 through R6:255. Therefore, Allen-Bradley SLC 500 PLCs
have 256 control registers.
In Figure 13-8, register R6:0 is the control register. In the control
register, two status bits are available to the PLC programmer. These
bits are the enable bit (R6:0/EN) and the done bit (R6:0/DN). The
enable coil (R6:0/EN) is energized when the BSL instruction is on.
The done coil (R6:0/DN) is energized when the BSL instruction has
shifted all bits as specified by the length. The contacts associated with
these bit coils can be used to turn on or turn off other PLC instructions
or output devices.
The reset (RES) instruction can be used to reset the BSL instruc-
tion. In Figure 13-8, the reset button is energized when switch I:1/2 is
closed. Then, the BSL instruction resets to position zero. Example 13-2
illustrates how to use the BSL instruction in ladder logic diagrams.
Bit Shift Left (BSL) Instruction
0000
0001
0002
0003
0004
I:1
1
0
End
BSL
Bit shift left
File #B3:0
Control R6:0
Bit Address B3:0/0
Length 7
LPB
R6:0
UL
B3:0
I:1
0
MOV
Move
Source 43690
AAAAh
Dest #B3:0
Length 43604
MOVE
Reset
EN
DN
RES
I:1
2
R6:0
RES
Figure 13-8. Bit shift left (BSL) instruction for the Allen-Bradley SLC 500 PLC.