Copyright Goodheart-Willcox Co., Inc. Chapter 9 PLC Counter Instructions 201 Complete each of the following sentences with the correct word(s). 12. The counter done bit for count up instruction C5:0 is addressed as _____. 13. The preset value for counter C5:0 is in register _____. 14. When an input instruction to the count up instruction is closed, the _____ coil energizes. 15. You must use the _____ instruction to reset a count up instruction. 16. The content of an accumulated register for the count up instruction is _____ for every low-to-high counter input switch transition. 17. The counter done bit for the count down instruction C5:0 is addressed as _____. 18. The content of an accumulated register for the count down instruction is _____ for every low-to-high counter input switch transition. 19. The accumulated value for counter instruction C5:0 is in the _____ register. 20. When an input instruction to the count down instruction C5:0 is closed, the _____ coil energizes. 21. You must use the _____ instruction to reset a count down instruction. 22. Data files _____ through _____ can be used for counter instructions. 23. When the content of the count up registers C5:0.PRE and C5:0.ACC are equal, the _____ coil energizes. 24. Allen-Bradley PLC count up (CTU) and count down (CD) instructions count whenever the counter input device changes _____. Specify if the following statements are true or false. 25. There are two types of PLC counter instructions. 26. The content of an accumulated register in the count up instruction increments whenever there is a low-to-high counter input switch transition. 27. The content of an accumulated register in the count down instruction decrements whenever there is a low-to-high counter input switch transition. 28. The accumulated register for counter instruction C5:0 is addressed as C5:0.ACC. 29. The count up instruction C5:0 in a fixed SLC 500 PLC uses two sixteen bit registers. 30. Internal bit C5:0/CU is on when the input to the count up instruction C5:0 is open. 31. Internal bit C5:0/CD is on when the input to the count up instruction C5:0 is closed. 32. The counter done bit for the counter instruction C5:1 is addressed as C5:1/DN. 33. PLC counter functions are similar to PLC timer functions, except that they do not use the internal clock in the PLC’s central processing unit. 34. The C5:0/DN flag is energized whenever the content of C5:0.ACC register is equal to or greater than the content of C5:0.PRE register. Using the counter instructions, draw the PLC ladder logic diagram for the following problems. 35. Output is to be turned on when count A goes from 12 down to 0 and when either count B goes up to 8 or count C has gone all the way from 10 down to 0. One switch resets the entire process. 36. Output turns on when either A counts up to 9, or B counts down to 7. 37. When you close the master switch (MSW), the following process will start. A. Motor number one runs for 3 seconds. B. Then motor number two runs for 5 seconds. C. Finally, the bell rings three times within 6 seconds.