Chapter 13 PLC Logic and Bit Shift Instructions 285
Example 13-3
Figure 13-12 displays the PLC ladder logic diagram for Exam-
ple 13-3. Figure 13-13 displays the bit data file for Example 13-3.
Notice that bit three (B3/3) is set to one.
TON
Timer On Delay
Timer T4:0
Time base 0.1
Preset 40
Accum 0
EN
DN
0000
0006
0007
0002
0003
0004
0005
0001
Switch
T4:0
I:1/0
0 DN
DN
Green_PLT
B3:0
BSR
Bit shift right
File #B3:0
Control R6:0
Bit address B3:0/3
Length 4
EN
DN
T4:0
R6:0
UL
Red_PLT
O:2
0
3
B3:0
3
White_PLT
O:2
1
2
B3:0
2
O:2 B3:0
1
RES
R6:0 I:1
1
RES
END
Example 13-3
Reset
Figure 13-12. PLC ladder logic diagram for Example 13-3.