Copyright Goodheart-Willcox Co., Inc. Chapter 9 PLC Counter Instructions 189 9.1 PLC Counter Instructions Programming a PLC counter is similar to programming a PLC timer. The PLC counter instruction can have either a double input or a single input. A double-input counter requires two inputs. One input signal is used to enable the counter, and the other input counts the number of pulse signals. These signals can be either high-to-low pulse (trailing-edge trigger) or low-to-high pulse (leading-edge trigger). For one input to both enable and count the signals or pulses, a single-input counter is used. r Like timer instructions, counter instructions can be displayed in either the block format or the coil format. In this chapter, you will study single-input counter instructions that are displayed in the block format. The Allen-Bradley SLC 500 series PLC uses one input for its counter instructions. Counters must be connected to an input device. When the input changes state, either from open to closed or from closed to open, the counter increments or decrements. Two different types of counter instructions are available in PLCs: count up and count down. The count up instruction causes the accumulated register’s value to increment (count up) whenever the counter input device changes state. The count down instruction causes the accumulated register’s value to decrement (count down) whenever the counter input device changes state. 9.2 PLC Counter Instruction Registers In Allen-Bradley SLC 500 series PLCs, counter instruction addresses can be C5:0 to C5:255. Therefore, theoretically, an Allen-Bradley SLC 500 series PLC can have up to 256 counter instructions. In practice, the number of counter instructions is limited by the amount of RAM memory in the PLC system. This is similar to the limitation on the number of timer instructions. Every Allen-Bradley SLC 500 series counter instruction has three 16-bit registers. These registers are: • Preset register. • Accumulated register. • Status register. For example, counter instruction C5:0 has the preset register C5:0.PRE, the accumulated register C5:0.ACC, and a status bit register. Figure 9-1 displays an Allen-Bradley SLC 500 count up instruction and a count down instruction. 0000 0001 0002 CTU Count up Counter C5:0 Preset 10 Accum 0 End CU DN CD DN CTD Count down Counter C5:1 Preset -15 Accum 0 Switch_1 0 I:0 Switch_2 1 I:0 Goodheart-Willcox Publisher Figure 9-1. Allen-Bradley SLC 500 count up and count down instructions.