Copyright Goodheart-Willcox Co., Inc. 190 Programmable Logic Controllers: Hardware and Programming The preset register (C5:0.PRE) is used to hold the preset counter number. The accumulated register (C5:0.ACC) holds the accumulated counter number. The status register holds flag bits that are used by the PLC to keep track of the operation of counter C5:0. Two flag bits are available to the PLC programmer: the count bit and the done bit C5:0/DN. The count bit for the count up instruction (C5:0/CU) or for the count down instruction (C5:0/CD) is enabled every time the counter counts up or down. These bits are similar to the enable bits (EN) in the timers. When the counter input contact is enabled, the count bit coil is energized. The done bit (C5:0/DN) becomes enabled when the accumulated number equals the preset number. The counter accumulated registers in Allen-Bradley SLC 500 PLCs are 16-bit registers. Each 16-bit register can hold a maximum positive number 7FFFh (+32,767 decimal) or a maximum negative number 8000h (–32,768 decimal). After the positive number in a count up instruction has incremented to +32,767 decimal, it starts over at –32,768 decimal and its overflow bit turns on. The overflow bit (OV) signals an error state in which the number does not fit in the 16-bit register. Also, when the negative number in a count down instruction decrements past –32,768 decimal, its underflow bit (UN) turns on. The underflow bit (UN) signals an error state in which the number to be stored is smaller than the 16-bit register can specify. Table 9-1 contains a brief description for counter-up (CTU) and counter-down (CTD) user-accessible registers and status bits. An additional status bit, called the update accumulator bit (UA), is used with high-speed counter (HSC) instructions. However, Allen-Bradley SLC 500 series PLCs do not utilize high-speed counter (HSC) instructions, so PLC high-speed counters are not discussed in this text. Goodheart-Willcox Publisher Table 9-1. SLC 500 counter instruction registers and status bits. Registers and Bits Register Address Description Preset register C5:0.PRE, C5:1.PRE, … Holds the preset counter number. Accumulated register C5:0.ACC, C5:1.ACC, … Holds the present count. Status register Holds the status flag bits: EN, TT, and DN. Count up bit C5:0/CU, C5:1/CU, … Enabled whenever the counter counts up. Count down bit C5:0/CD, C5:1/CD, … Enabled whenever the counter counts down. Done bit C5:0/DN, C5:1/DN Enabled whenever the content of the accumulated register is equal to or greater than the content of the preset register. 9.3 PLC Count Up Instructions In the count up instruction, the accumulated register increments whenever the counter input device changes state. Figure 9-2 displays a count up instruction that is connected to a normally open (NO) input device. Goodheart-Willcox Publisher Figure 9-2. PLC count up instruction. 0000 0001 0002 CTU Count up Counter C5:0 Preset 10 Accum 0 End CU DN RES Pushbutton 1 I:0 Switch 0 I:0 C5:0